Recent improvements for amplifiers used in analog signal applications such as analog to digital conversion include the use of telescopic amplifiers. Telescopic amplifiers provide relatively high frequency response with relatively low power. These telescopic amplifiers are therefore attractive for a variety of applications, particularly and increasingly for portable devices where low power is an important requirement. In an application, within a pipelined analog to digital converter (“ADC”) circuit topology, telescopic amplifiers are increasingly used as the residue amplifier. In the pipelined ADC, for each of a plurality of stages, the analog input signal is converted to one or more digital bits that approximate a magnitude of the analog signal, e.g. the input signal is quantized. The digital bits of the output are then converted back to an analog signal using a digital to analog converter (DAC), and the converted quantized signal, now an analog voltage corresponding to the quantized value, is subtracted from the input signal. These functions are commonly performed using a switched capacitor circuit known as a “MDAC”, or multiplying digital to analog converter. The residue, which is the difference between the input signal and the analog to digital converted version of the quantized digital output signal, is then amplified in a residue amplifier. The amplified residue signal is used as the input signal for the next stage of the pipelined ADC converter. In this manner the input analog signal is successively converted to a multiple bit digital representation in pipelined ADC stages. While other amplifiers can be used in the pipelined ADC, telescopic amplifiers are increasingly used as the residue amplifier. Additional discussion of telescopic amplifiers may be found, for example, in U.S. Pat. No. 6,529,070, entitled “Low Voltage Broadband Telescopic Amplifier”, which is co-owned with the present application, and which is hereby incorporated in its entirety herein by reference.
FIG. 1 depicts, in an example simplified circuit diagram, a telescopic operational amplifier circuit 10 of the prior art. In FIG. 1, circuit 10 has a terminal INP for receiving a positive differential signal arranged with a terminal INM for receiving a complementary differential input signal. An input stage is formed by transistor MNINP, with a gate coupled to the positive input terminal INP, and transistor MNINM having a gate coupled to the complementary input terminal INM. The input stage transistors MNINP and MNINM have their respective source regions coupled together to form a common source terminal. The common source from the two input transistors MNINM and MNINP is coupled to the drain of the tail current transistor, MNTAIL.
A cascode output stage is formed by transistors MNCASP and MNCASM. Each of these output stage transistors has a gate coupled to the cascode bias voltage CAS_BIAS. The current sources IP and IM supply bias current to the drain terminals of the transistors MNCASP and MNCASM. These current sources IP=IM=I, where I is the bias current of the circuit stage. Each of the output stage transistors MNCASP and MNCASM has a source that is coupled to the drain of the respective one of the input stage transistors MNINP and MNINM.
The circuit 10 has differential output terminals OUTP and OUTM for transmitting positive and complementary differential output signals to the next stage of the circuit. The output terminals OUTP and OUTM are coupled to the drains of MNCASP and MNCASM, the differential output transistors. In order to illustrate the operation of the circuit 10, the sampling portion of the next stage circuit 20 is depicted. A switched capacitor circuit, the sample stage circuit 20 includes the clocked switches implemented by transistors MNSWIP and MNSWIM. When the clock signal CLK is true, or at a high voltage, the gates of these switches are coupled to the CLK signal, and the transistors MNSWP and MNSWM couple the output terminals OUTP and OUTM to the sample capacitors CP and CM in the switched capacitor sample circuit 20. The sampled values are then available for a later transfer into the next stage circuit (not shown).
In FIG. 1, a common mode feedback circuit 30 is depicted. This common mode feedback circuit 30 is another switched capacitor circuit formed of transistors MN1, MN3, MN5, and MN2, MN4, MN6, and capacitors CRFP, CRFM, CCMFBP, CCMFBN. The inputs are common mode reference signals REFCM and a bias signal BIAS. The clock signal CLK and the inverted clock signal CLK_BAR are non-overlapping, complementary clocking signals. When the CLK_BAR signal is high, or true, the transistors MN2, MN4 and MN6 act as closed switches and the capacitors CRFP and CRFM have the voltage REFCM-BIAS across them. When the CLK signal is true, or high, the common mode feedback capacitors CCMFBP and CCMFBN are shorted to the capacitors CRFP and CRFM, which store the common mode reference voltages. Input terminal REFCM fixes the output common mode of the amplifier to a common mode reference input voltage. The differential output terminals OUTP and OUTM of the telescopic amplifier are coupled to the capacitors CCMFBP and CCMFBM to form the common mode feedback path of the telescopic amplifier 10. The common mode feedback circuit has an output at node CMOUT.
The gate of the tail current transistor MNTAIL is coupled to the common mode feedback circuit at node CMOUT. In this manner a common mode settling current (shown as Icm in the figure) flows through the tail transistor MNTAIL. The common mode settling current Icm should be equally shared between the two branches of the differential circuit, shown as currents Icm/2 in FIG. 1. Differential settling current Idiff is also shown. Note that in the circuit diagram of FIG. 1, the input stage and output stage transistors MNINP, MNINM, MNCASP, MNCASM, are each illustrated as formed using N type MOSFET transistors, and the tail transistor MNTAIL is also shown as formed using an N-type MOSFET transistor. However, one skilled in the art will recognize that other transistor types including P-type MOSFET transistors could be used instead of the N-type MOSFET transistors shown in this illustrative example, the substitution could be made to replace the N type MOSFET transistors with P type MOSFET transistors, and in other respects, the circuit topology and functions of the telescopic amplifier circuit 10 would remain the same.
The telescopic amplifier circuit 10 of FIG. 1 may be used with a pre-amplifier (not shown for simplicity) in a residue amplifier for an ADC circuit to provide relatively high gain bandwidth at relatively low power. However, the common mode settling characteristics of the prior art telescopic amplifier 10 shown in FIG. 1 are poor. The common mode feedback loop bandwidth is low when compared to the differential bandwidth; typically it is ½ to ⅓rd of the differential bandwidth.
As can be seen in FIG. 1, the next stage sampling circuit 20 will receive the common mode and differential current when CLK is high. The transistors MNSWP and MNSWP in sampling circuit 20, also shown here as N-type MOSFET transistors, have resistances which, ideally, are perfectly matched. However in an actual physical circuit the resistances of these two transistors will not match perfectly due to process, temperature and voltage variations (PVT). Due to the resistance mismatch of these sampling transistors, poor common mode current settling may lead to an error in the sampling circuit in the next stage. That is, a differential current error may occur due to the presence of a common mode settling current.
The common mode feedback loop of the circuit of FIG. 1 is effectively a single pole system. Using a circuit analysis that neglects differential mode signals and that is for the common mode signals only, the common mode feedback loop gain expression for the structure in FIG. 1 is:LPG=(β*Gmntail/(2CLs+gd))  (Equation 1)                Where: β=CCM/CCM+CTAIL, and gd=the output conductance of one arm of the telescopic structure, which is very small, and Gmntail is the transconductance of the tail transistor MNTAIL.        
From Equation 1, it can be seen that the transfer function for the loop gain, for common mode, is a single pole system with a pole located at:P1=gd/CL(radians/second).  (Equation 2)
P1 is the single, dominant pole in the common mode feedback transfer function. In this analysis, the cascade pole and the pole due to the input transistors were neglected, as these poles will be fractions of fT of the corresponding transistors, and will be located far from the common mode feedback unity gain bandwidth, ωugh.
The capacitance CCM can be determined as:CCM=(CCMFBP+CCMFBM+CRFP+CRFM), where CRFP=CRFM and CCMFBP=CCMFBM.  (Equation 3).
The tail capacitance CTAIL can be determined as:CTAIL=CROUTP+CGDSTAIL+CGDMILLER,  (Equation 4)where CROUTP is a parasitic routing capacitance (as indicated by the dashed lines used to represent it in FIG. 1), and CGDSTAIL and CGDMILLER are the gate to source capacitance and gate to drain (including Miller effect) capacitances of the tail transistor MNTAIL in FIG. 1.
The load capacitance CL can be determined as:CL=COUTP+CP,COUTM+CM,  (Equation 5)where: COUTP=COUTM are the parasitic routing capacitances at the output of the telescopic amplifier, (as shown by the dashed lines used to draw these capacitors in FIG. 1) and the capacitors CM and CP, as shown in FIG. 1, are part of the sampling circuit 20 that is for the next stage. The sampling time constant is small compared to the time 1/ωugb.
Taking these factors into account, then, the unity gain bandwidth ωugb for the common mode feedback loop can be determined as:ωugb=βGmntail/2CL.  (Equation 6)
As discussed above, the sampling transistors MNSWIP and MNSWIM of the next stage sampling circuit 20 in FIG. 1 may have resistances that are not equal. The resistances may be mismatched due to process variations, temperature dependence variations, and/or a variation in voltage swing. If the common mode settling for the circuit 10 is poor, then a current due to common mode settling may produce a differential voltage across these sampling switches and generate a sampling error in the sampling capacitors CP and CM. This error may not be acceptable in a particular circuit, in the high resolution residue stage for a pipelined ADC circuit, for example. The common mode settling current may appear as a differential current to the sampling stage, causing error.
One known approach to this problem is to try to precisely match the sampling transistor devices, MNSWIP and MNSWIM, to reduce the resistance mismatch, by tightly controlling the process, voltage and temperature (PVT) corner. This is very difficult to do in advanced semiconductor processes, and can reduce device yield, increasing the per device costs. Another known approach is to try and reduce the common mode current by improving the common mode feedback settling. The unity gain bandwidth ωugb could be increased but at the cost of extra power in the telescopic structure. However, increasingly the applications for the telescopic amplifier are for portable devices, which are often battery powered devices, thus this increase in power consumption is also undesirable.
Improvements in the common mode settling characteristics for telescopic amplifiers are therefore needed to address the deficiencies and the disadvantages of the known prior approaches. Solutions are needed that do not require additional power, and which do not negatively impact the noise performance and the differential settling performance of the telescopic amplifier circuits.